Testing an integrated circuit device or a packaged component including circuitry (generally referred to as a device under test (DUT)) at the time it is manufactured and before it is incorporated into a next level assembly is generally necessary to ascertain the functionality of the DUT. A microprocessor, for instance, should be tested before it is incorporated into a next level assembly to avoid the cost of discarding the whole assembly, or to avoid a costly diagnosis and repair after it is assembled into the next level assembly.
Traditionally, microprocessors and integrated circuit devices have been subjected to functional testing using an external tester. These external testers contain a large memory that stores test data patterns of ones and zeros used as inputs to the microprocessor along with patterns of correct outputs expected from the microprocessor. The benefits of functional testing include testing the device in the native mode of operation, making speed testing easier, and providing collateral coverage of faults not modeled during the fault grading process. The drawback of functional testing is that the external tester performance has to keep up with microprocessor performance improvements, and the writing of test data patterns for functional testing can take as much as 60 to 100 man-years. Also, functional testing generally increases tester data volume and the application time require to develop the test methodology.
To circumvent the problem of increased tester data volume and application time, a special test mode is designed into the microprocessor circuitry. When this mode of operation is selected, the internal state of nodes in the microprocessor circuitry can be accessed, initialized and controlled directly from the tester without having to run through the functional inputs and outputs that are used in normal operation mode. Using this type of test mode to test the microprocessor accomplishes the testing of the structure of the microprocessor, and not the whole function of the microprocessor. Testing the microprocessor using the special test mode is generally known as “structural testing”. Structural testing can considerably reduce the test data volume and application time, and permits using automatic tools to program the tester, which in turn reduces the time required to write test data patterns. However, structural testing targets fault models and not functionality, and are generally small in number.
To overcome this limitation, techniques such as Built-In Self-Test (BIST) have been proposed, which apply a large volume of structural testing to the device. BIST uses random data patterns to test the DUT in the test mode. When using random data patterns in the test mode, the state elements are configured in a long daisy chain, such that the test data moves serially from one state element to another, eventually coming out of an external pin in the DUT. The term “state elements” in this document refers to parts of the microprocessor circuit that potentially hold data for at least one clock cycle. The use of these random data patterns considerably reduces the volume of stored bits on a tester, thereby significantly simplifying and reducing the cost of testing the DUTs.
BIST also uses signature analyzers to compress the test results into a single smaller pattern or “signature”, to reduce the amount of tester memory and circuitry required. The signature is then analyzed to determine whether the DUT is free of structural defects. For BIST, the random pattern generator and the signature analyzer circuitry are built into the DUT itself. This eliminates the need for using an external tester to test the DUT.
To apply random data patterns, 0's and 1's are used to energize various parts of circuitry in the DUT. In some cases, however, the application of random data patterns can set up electrically undesirable configurations (undesirable bit segments). For example, applying a non-functional scan test can cause drive fights among multiple drivers sharing a common bus resulting in electrical short circuit from the power supply to ground. This configuration, also referred to as “bus contention”, can potentially cause burnout or reliability issues in the DUT. Such configurations are generally ruled out by design in the functional mode, but it is extremely difficult and expensive to guarantee that they will not arise during the application of random data patterns.
Another side effect of using a non-functional testing such as BIST is some of the state elements in the design may be a critical path. Including these state elements in the scan chain can cause a significant delay in a signal propagating through, or serially coming in and out of these state elements, and this may not be acceptable. To circumvent this problem, these state elements may not be scanned, that is, not configured to be part of a serial shift register in test mode. Not scanning a state element results in a loss of control over the value at its output node (a specific kind of state element) during a test, when random data patterns are being shifted into the scanned elements. This can result in a non-deterministic value (unpredictable bit) at the output node of the non-scan state element, which can corrupt the signature being computed in a BIST signature analyzer. This result of a non-deterministic value at the output node is generally referred to as “X-generation”.
Generally, for structural testing to succeed, all of the internal state/storage elements must be considered in the scan chain. Leaving some elements out in the test mode can result in lack of controllability and observability. Implementing a pattern correction and X-masking functionality on a structural tester to circumvent the bus contention and the X-generation problems inherent in random patterns generally requires extensive changes to tester architecture and cannot be implemented easily, especially when the current cycle time for new external testers is around 5 to 6 years. Implementing a structural test that can overcome the bus contention and the X-generation problems on a chip generally requires increasing the die size, design effort, and hardware overhead.
Therefore there is a need for a structural test that can be implemented on a chip to circumvent the bus contention problems and the X-generation problems during testing of a DUT, yet can provide the advantages of the random pattern testing such as reduced design overhead, controllability and observability of the DUTs during testing without increasing the die size, design effort, and overhead.